Electronic Design

ATE – Design for Test – Putting Memory to the Test in Nanometer Designs

Memory test at-speed isn't easy but can be achieved by balancing test selection, area overhead, and test-time constraints. The semiconductor industry has intensified its focus on yield issues to meet ...
Semiconductor Engineering

Automate Memory Test Through A Shared Bus Interface

The use of memory-heavy IP in SoCs for automotive, artificial intelligence (AI), and processor applications is steadily increasing. However, these memory-heavy IP often have only a single access point ...
Semiconductor Engineering

New Error Correcting Code And Non-Volatile Memory Options For Memory BIST

Tessent MemoryBIST from Siemens EDA provides a complete solution for at-speed test, diagnosis, repair, debug and characterization of embedded memories. Leveraging a flexible hierarchical architecture, ...
EDN

Embedded SRAM test and repair moves on-chip

SAN MATEO, Calif. — With the rollout of its Star Memory System, an on-chip test and repair mechanism for embedded SRAM, memory compiler specialist Virage Logic Corp. is making good on its promise to ...
Electronic Design

Putting Memory to the Test in Nanometer Designs

Memory test at-speed isn�t easy but can be achieved by balancing test selection, area overhead, and test-time constraints. The semiconductor industry has intensified its focus on yield issues to ...