When we verify a System on Chip (SoC) that embeds microprocessors with several digital peripherals, and possibly analog blocks as well, we want to check all the implemented features and possible ...

The complexity of system on chips (SoCs) continues to grow rapidly with the integration of more functionality onto a single chip. As a result, traditional verification methodologies struggle to keep ...

NATICK, Mass.--(BUSINESS WIRE)--MathWorks today announced that HDL Verifier provides support for the Universal Verification Methodology (UVM) starting with Release 2019b, which is currently available.

We have all been witnesses to the rapid improvements of the iPhone processor chip every year. With the iPhone 8 featuring the newest A11 Bionic at 10 nm FinFET with 4.3 billion transistors, I can’t ...

The GPIO (General Purpose Input/Output) core design provides a general purpose input/output interface to a 32-bit On-chip Peripheral Bus (OPB). This GPIO core requires simple output and/or input ...

The Formal Property Verification (FPV) methodology often gets used in the last step of verification flow, after much time spent building a complex random constrained UVM (Universal Verification ...

In a System-on Chip(SoC),a general interrupt process works as follows: Interrupt is triggered by a certain system event or interrupt source. Interrupt is detected by system’s peripheral module, which ...

It’s time for a frank discussion on the future of UVM. Given how UVM usage has grown and the number of teams that rely on it, I think this conversation has been a long time coming. Is continuing to ...

Analog/mixed-signal content in SoCs needs to be modeled in a similar way as the digital content but does UVM make sense for pure analog? Perhaps not. As SoC complexity has grown, so too has the need ...

The key rule for chip design and verification is that bugs must be found and fixed as early in the development process as possible. It is often said that catching a bug at each successive project ...