Philippe Luc, director of verification at Codasip, talked to students of the UK Electronics Skills Foundation (UKESF) about what it is like to be a verification engineer. On one hand the UKESF ...

Groundbreaking benefits of using artificial intelligence in design verification. How SHAPley values can help engineers optimize debugging in design verification. Achieving low-latency SoC ...

Semiconductor Engineering sat down to discuss the implications of having an executable specification that drives verification with Hagai Arbel, chief executive officer for VTool; Adnan Hamid, chief ...

Accelerates design and verification with domain-scoped agentic, AI-driven workflows and configurable human expertise for faster, trusted RTL sign-off ...

Tell us a little about your professional and/or educational background. I did my bachelors’ degree in electrical and electronics in India. After graduating, I worked at Intel for a year as a design ...

Designing the hardware-software interface. Dealing with "bytes enables" in RTL verification. Automating the HSI design process across the entire dev team. The hardware-software interface (HSI) holds ...

In partnership with the Israel Tech Challenge, Apple is co-hosting an event at its Israel headquarters to discuss a new Design Verification Engineering course. This course will be a ten month-long ...

Virtusa has acquired Bengaluru-based SmartSoC Solutions for an undisclosed sum to deepen chip design, verification and ...

While a working device that meets all functional specifications is a chip design project group’s No. 1 goal, many designers wake up covered in sweat worrying about a dead-on-arrival chip. No matter ...

Siemens announced the Questa One Agentic Toolkit, which brings domain-scoped agentic AI workflows to its Questa One smart verification software portfolio to accelerate creation, verification planning, ...